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rev: 1.03a 5/2003 1/36 ? 2001, giga semiconductor, inc. specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. nobl is a trademark of cypress semiconducto r corp.. ntram is a trademark of samsung el ectronics co.. zbt is a trademark of inte grated device technology, inc. gs8162z18a(b/d)/gs8162z 36a(b/d)/gs8162z72a(c) 18mb pipelined and flow through synchronous nbt sram 300 mhz ? 150 mhz 2.5 v or 3.3 v v dd 2.5 v or 3.3 v i/o 119, 165, & 209 bga commercial temp industrial temp preliminary features ? nbt (no bus turn around) functionality allows zero wait read-write-read bus utilization; fully pin-compatible with both pipelined and flow through ntram?, nobl? and zbt? srams ? 2.5 v or 3.3 v +10%/?10% core power supply ? 2.5 v or 3.3 v i/o supply ? user-configurable pipeline and flow through mode ? zq mode pin for user-selectable high /low output drive ? ieee 1149.1 jtag-compatible boundary scan ? on-chip write parity checkin g; even or odd selectable ? on-chip parity encoding and error detection ? lbo pin for linear or interleave burst mode ? pin-compatible with 2m, 4m, and 8m devices ? byte write operation (9-bit bytes) ? 3 chip enable signals for easy depth expansion ? zz pin for automatic power-down ? jedec-standard 119-, 165-, or 209-bump bga package functional description the gs8162z18a(b/d)/36a(b/d)/72a(c) is an 18mbit synchronous static sram. gsi's nbt srams, like zbt, ntram, nobl or other pipelined read/double late write or flow through read/single late write srams, allow utilization of all available bus bandwidth by eliminating the need to insert deselect cycles when the device is switched from read to write cycles. because it is a synchronous devi ce, address, data inputs, and read/write control inputs are captured on the rising edge of the input clock. burst order control (lbo ) must be tied to a power rail for proper operation. asynchronous inputs include the sleep mode enable (zz) and outp ut enable. output enable can be used to override the synchronous control of the output drivers and turn the ram's output drivers off at any time. write cycles are internally self- timed and initiated by the rising edge of the clock input. this feature eliminates complex off- chip write pulse generation required by asynchronous srams and simplifies input signal timing. the gs8162z18a(b/d)/36a(b/d)/72a(c) may be configured by the user to operate in pipeline or flow through mode. operating as a pipelined synchronous device, in addition to the rising-edge-triggered registers that capture input signals, the device in corporates a rising edge triggered output register. for read cycles, pipe lined sram output data is temporarily stored by the edge-triggered output register during the access cycle and then released to the output drivers at the next rising edge of clock. the gs8162z18a(b/d)/36a(b/d)/72a(c) is implemented with gsi's high performance cmos technology and is available in a jedec-standard 119-bump (x18 & x36), 165- bump (x18 & x36), or 209- bump (x72) bga package. parameter synopsis -300 -250 -200 -150 unit pipeline 3-1-1-1 t kq (x18/x36) t kq (x72) tcycle 2.5 2.8 3.3 2.5 3.0 4.0 3.0 3.0 5.0 3.8 3.8 6.7 ns ns ns curr (x18) curr (x32/x36) curr (x72) 335 390 495 280 330 425 230 270 345 185 210 270 ma ma ma flow through 2-1-1-1 t kq tcycle 5.0 5.0 5.5 5.5 6.5 6.5 7.5 7.5 ns ns curr (x18) curr (x32/x36) curr (x72) 230 270 345 210 240 315 185 205 275 170 190 250 ma ma ma
rev: 1.03a 5/2003 2/36 ? 2001, giga semiconductor, inc. specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. gs8162z18a(b/d)/gs8162z 36a(b/d)/gs8162z72a(c) preliminary gs8162z72 pad out 209-bump bga ? top view (package c) 1234567891011 a dqg dqg a e2 a adv a e 3adqbdqb b dqg dqg b cb gnc w ab bb fdqbdqb c dqg dqg b hb dnce 1ncb eb adqbdqb d dqg dqg v ss nc nc g nc nc v ss dqb dqb e dqpg dqpc v ddq v ddq v dd v dd v dd v ddq v ddq dqpf dqpb fdqcdqcv ss v ss v ss zq v ss v ss v ss dqf dqf g dqc dqc v ddq v ddq v dd mch v dd v ddq v ddq dqf dqf h dqc dqc v ss v ss v ss mcl v ss v ss v ss dqf dqf j dqc dqc v ddq v ddq v dd mch v dd v ddq v ddq dqf dqf k nc nc ck nc v ss cke v ss nc nc nc nc l dqh dqh v ddq v ddq v dd ft v dd v ddq v ddq dqa dqa m dqh dqh v ss v ss v ss mcl v ss v ss v ss dqa dqa n dqh dqh v ddq v ddq v dd mch v dd v ddq v ddq dqa dqa p dqh dqh v ss v ss v ss zz v ss v ss v ss dqa dqa r dqpd dqph v ddq v ddq v dd v dd v dd v ddq v ddq dqpa dqpe t dqd dqd v ss nc nc lbo pe nc v ss dqe dqe u dqd dqd nc a nc a nc a nc dqe dqe vdqddqdaaaa1aaadqedqe w dqd dqd tms tdi a a0 a tdo tck dqe dqe rev 10 11 x 19 bump bga ? 14 x 22 mm 2 body ? 1 mm bump pitch
rev: 1.03a 5/2003 3/36 ? 2001, giga semiconductor, inc. specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. gs8162z18a(b/d)/gs8162z 36a(b/d)/gs8162z72a(c) preliminary gs8162z72 bga pin description symbol type description a 0 , a 1 i address field lsbs and address counter preset inputs a i address inputs dq a dq b dq c dq d dq e dq f dq g dq h i/o data input and output pins b a , b b , b c ,b d, b e , b f , b g ,b h i byte write enable for dq a , dq b , dq c , dq d, dq e , dq f , dq g , dq h i/os; active low nc ? no connect ck i clock input signal; active high w i write enable. writes all enabled bytes; active low e 1, e 3 i chip enable; active low e 2 i chip enable; active high g i output enable; active low zz i sleep mode control; active high ft i flow through or pipeline mode; active low lbo i linear burst order mode; active low mch i must connect high mcl must connect low pe i parity bit enable; active low (hig h = x16/32 mode, low = x18/36 mode) cke i clock enable; active low bw i byte enable; active low zq i flxdrive output impedance control (low = low impedance [high drive], high = high impedance [low drive]) tms i scan test mode select tdi i scan test data in tdo o scan test data out tck i scan test clock v dd i core power supply v ss i i/o and core ground v ddq i output driver power supply
rev: 1.03a 5/2003 4/36 ? 2001, giga semiconductor, inc. specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. gs8162z18a(b/d)/gs8162z 36a(b/d)/gs8162z72a(c) preliminary 165 bump bga?x18 commom i/ o?top view (package d) 1234567891011 anc ae1 bb nc e3 cke adv a a aa bnc ae2ncba ck w g a anc b cncnc v ddq v ss v ss v ss v ss v ss v ddq nc dqpa c dnc dqb v ddq v dd v ss v ss v ss v dd v ddq nc dqa d enc dqb v ddq v dd v ss v ss v ss v dd v ddq nc dqa e fnc dqb v ddq v dd v ss v ss v ss v dd v ddq nc dqa f gnc dqb v ddq v dd v ss v ss v ss v dd v ddq nc dqa g hft mch nc v dd v ss v ss v ss v dd nc zq zz h j dqb nc v ddq v dd v ss v ss v ss v dd v ddq dqa nc j k dqb nc v ddq v dd v ss v ss v ss v dd v ddq dqa nc k l dqb nc v ddq v dd v ss v ss v ss v dd v ddq dqa nc l m dqb nc v ddq v dd v ss v ss v ss v dd v ddq dqa nc m n dqpb dnu v ddq v ss nc nc nc v ss v ddq nc nc n pncnc a atdi a1 tdo a a anc p rlbo nc a atms a0 tck a a a ar 11 x 15 bump bga?13 mm x 15 mm body?1.0 mm bump pitch
rev: 1.03a 5/2003 5/36 ? 2001, giga semiconductor, inc. specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. gs8162z18a(b/d)/gs8162z 36a(b/d)/gs8162z72a(c) preliminary 165 bump bga?x36 common i/o?top view (package d) 1234567891011 anc ae1 bc bb e3 cke adv a anc a bnc ae2bd ba ck w g a anc b c dqpc nc v ddq v ss v ss v ss v ss v ss v ddq nc dqpb c d dqc dqc v ddq v dd v ss v ss v ss v dd v ddq dqb dqb d e dqc dqc v ddq v dd v ss v ss v ss v dd v ddq dqb dqb e f dqc dqc v ddq v dd v ss v ss v ss v dd v ddq dqb dqb f g dqc dqc v ddq v dd v ss v ss v ss v dd v ddq dqb dqb g hft mch nc v dd v ss v ss v ss v dd nc zq zz h j dqd dqd v ddq v dd v ss v ss v ss v dd v ddq dqa dqa j k dqd dqd v ddq v dd v ss v ss v ss v dd v ddq dqa dqa k l dqd dqd v ddq v dd v ss v ss v ss v dd v ddq dqa dqa l m dqd dqd v ddq v dd v ss v ss v ss v dd v ddq dqa dqa m n dqpd dnu v ddq v ss nc nc nc v ss v ddq nc dqpa n pncnc a atdi a1 tdo a a anc p rlbo nc a atms a0 tck a a a ar 11 x 15 bump bga?13 mm x 15 mm body?1.0 mm bump pitch
rev: 1.03a 5/2003 6/36 ? 2001, giga semiconductor, inc. specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. gs8162z18a(b/d)/gs8162z 36a(b/d)/gs8162z72a(c) preliminary gs8162z36 pad out 119 bump bga ? top view (package b) 1234567 a v ddq aaaaav ddq b nc e 2 aadva e 3 nc c nc a a v dd aanc d dq c dqp c v ss zq v ss dqp b dq b e dq c dq c v ss e 1 v ss dq b dq b f v ddq dq c v ss g v ss dq b v ddq g dq c dq c b c ab b dq b dq b h dq c dq c v ss w v ss dq b dq b j v ddq v dd nc v dd nc v dd v ddq k dq a dq a v ss ck v ss dq a dq a l dq a dq a b d nc b a dq a dq a m v ddq dq a v ss cke v ss dq a v ddq n dq a dq a v ss a 1 v ss dq a dq a p dq a dqp a v ss a 0 v ss dqp a dq a r nc a lbo v dd ft ape t nc nc a a a nc zz u v ddq tms tdi tck tdo nc v ddq
rev: 1.03a 5/2003 7/36 ? 2001, giga semiconductor, inc. specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. gs8162z18a(b/d)/gs8162z 36a(b/d)/gs8162z72a(c) preliminary gs8162z18a pad out 119 bump bga ? top view (package b) 1234567 a v ddq aaaaav ddq b nc e 2 aadva e 3 nc c nc a a v dd aanc d dq b nc v ss zq v ss dq pa nc e nc dq b v ss e 1 v ss nc dq a f v ddq nc v ss g v ss dq a v ddq g nc dq b b b ancncdq a h dq b n c v ss w v ss dq a nc j v ddq v dd nc v dd nc v dd v ddq k nc dq b v ss ck v ss nc dq a l dq b nc nc nc b a dq a nc m v ddq dq b v ss cke v ss nc v ddq n dq b nc v ss a 1 v ss dq a nc p nc dq pb v ss a 0 v ss nc dq a r nc a lbo v dd ft ape t nc a a nc a a zz u v ddq tms tdi tck tdo nc v ddq
rev: 1.03a 5/2003 8/36 ? 2001, giga semiconductor, inc. specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. gs8162z18a(b/d)/gs8162z 36a(b/d)/gs8162z72a(c) preliminary bpr1999.05.18 gs8162z18/36 119-bump and 165-bump bga pin description symbol type description a 0 , a 1 i address field lsbs and address counter preset inputs a i address inputs dq a dq b dq c dq d i/o data input and output pins b a , b b , b c , b d i byte write enable for dq a , dq b , dq c , dq d i/os; active low nc ? no connect ck i clock input signal; active high cke i clock enable; active low pe i parity bit enable; active low (hi gh = x16/32 mode, low = x18/36 mode) w i write enable; active low e 1 i chip enable; active low e 3 i chip enable; active low e 2 i chip enable; active high g i output enable; active low adv i burst address counter advance enable; active high zz i sleep mode control; active high ft i flow through or pipeline mode; active low lbo i linear burst order mode; active low zq i flxdrive output impedance control (low = low impedance [high drive], high = high impedance [low drive]) tms i scan test mode select tdi i scan test data in tdo o scan test data out tck i scan test clock v dd i core power supply v ss i i/o and core ground v ddq i output driver power supply
rev: 1.03a 5/2003 9/36 ? 2001, giga semiconductor, inc. specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. gs8162z18a(b/d)/gs8162z 36a(b/d)/gs8162z72a(c) preliminary functional details clocking deassertion of the clock enable (cke ) input blocks the clock input fr om reaching the ram's internal circuits. it may be used to suspend ram operations. failure to observ e clock enable set-up or hold requirem ents will result in erratic operation. pipeline mode read and write operations all inputs (with the exception of output enab le, linear burst order and sleep) are synchr onized to rising clock edges. single c ycle read and write operati ons must be initiated with the advance/load pin (adv) held low, in order to load the new address. device activation is accomplished by asserting al l three of the chip enable inputs (e 1 , e 2, and e 3 ). deassertion of an y one of the enable inputs will deactivate the device. read operation is initiated when the following conditions are satisfied at the rising edge of clock: cke is asserted low, all three chip enables (e 1 , e 2, and e 3 ) are active, the write enable input signals w is deasserted high, and adv is asserted low. the address presented to the address inputs is latched into the address register an d presented to the memory co re and control logic. the co ntrol logic determines that a read access is in progress and allows th e requested data to propagate to the input of the output regist er. at the next rising edge of clock the read data is allowed to propagate through the output register and onto the output pins. write operation occurs when the ram is selected, cke is active, and the write input is sampled low at the rising edge of clock. the byte write enable inputs (b a , b b , b c, and b d ) determine which bytes will be written. all or none may be activated. a write cycle with no byte write inputs active is a no-op cycle. th e pipelined nbt sram provides double late write functionality, matching the write command versus data pipe line length (2 cycles) to the read comman d versus data pipeline length (2 cycles). a t the first rising edge of clock, enable, write, byte write(s), and address are registered. the data in associated with that addr ess is required at the third rising edge of clock. flow through mode read and write operations operation of the ram in flow through mode is very similar to op erations in pipeline mode. activation of a read cycle and the use of the burst address counter is identical. in flow through mode the device may begin driving out new data immediately after new address are clocked into the ram, rather than holding new data until the following (second) clock edge. therefore, in flow through mode the read pipeline is one cycle shorter than in pipeline mode. write operations are initiated in the same way, but differ in that the write pipeline is one cy cle shorter as well, preserving the ability to turn the bus from reads to writes without inserting any dead cycles. while the pipelined nbt rams implement a double late write protocol in flow through mode a single late write protocol mode is observed. therefore, in flow through mode, address and control are registered on the first rising edge of clock and data in is required at the data input pins at the second risin g edge of clock. function w b a b b b c b d read h x x x x write byte ?a? l l h h h write byte ?b? l h l h h write byte ?c? l h h l h write byte ?d? l h h h l write all bytes l l l l l write abort/nop l h h h h
rev: 1.03a 5/2003 10/36 ? 2001, giga semiconductor, inc. specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. gs8162z18a(b/d)/gs8162z 36a(b/d)/gs8162z72a(c) preliminary synchronous truth table operation type address e 1 e 2 e 3 zz adv w bx g cke ck dq notes deselect cycle, power down d none h x x l l x x x l l-h high-z deselect cycle, power down d none x x h l l x x x l l-h high-z deselect cycle, power down d none x l x l l x x x l l-h high-z deselect cycle, continue d none x x x l h x x x l l-h high-z 1 read cycle, begin burst r external l h l l l h x l l l-h q read cycle, continue burst b next x x x l h x x l l l-h q 1,10 nop/read, begin burst r external l h l l l h x h l l-h high-z 2 dummy read, continue burst b next x x x l h x x h l l-h high-z 1,2,10 write cycle, begin burst w external l h l l l l l x l l-h d 3 write cycle, continue burst b next x x x l h x l x l l-h d 1,3,10 nop/write abort, begin burst w none l h l l l l h x l l-h high-z 2,3 write abort, continue burst b next x x x l h x h x l l-h high-z 1,2,3,10 clock edge ignore, stall current x x x l x x x x h l-h - 4 sleep mode none x x x h x x x x x x high-z notes: 1. continue burst cycles, whether read or write, use the same control inputs. a deselect continue cycle can only be entered into if a deselect cycle is executed first. 2. dummy read and write abort can be consider ed nops because the sram performs no ope ration. a write abort occurs when the w pin is sampled low but no byte write pins are active, so no write operation is performed. 3. g can be wired low to minimize the number of control signals prov ided to the sram. output drivers will automatically turn off du ring write cycles. 4. if cke high occurs during a pipelined read cycle, the dq bus will remain active (low z). if cke high occurs during a write cycle, the bus will remain in high z. 5. x = don?t care; h = logic high; l = logic low; bx = high = all byte write signals are high; bx = low = one or more byte/write signals are low 6. all inputs, except g and zz must meet setup and hold times of rising clock edge. 7. wait states can be inserted by setting cke high. 8. this device contains circuitry that ensur es all outputs are in high z during power-up. 9. a 2-bit burst counter is incorporated. 10. the address counter is incriminat ed for all burst continue cycles.
rev: 1.03a 5/2003 11/36 ? 2001, giga semiconductor, inc. specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. gs8162z18a(b/d)/gs8162z 36a(b/d)/gs8162z72a(c) preliminary deselect new read new write burst read burst write w r b r b w d d b b w r d b w r d d pipelined and flow through read write control state diagram current state (n) next state (n+1) transition ? input command code key notes 1. the hold command (cke low) is not shown because it prevents any state change. 2. w, r, b, and d represent input command codes as indicated in t he synchronous truth table. clock (ck) command current state next state ? n n+1 n+2 n+3 ??? current state and next state definition for pipelined and flow th rough read/write co ntrol state diagram w r
rev: 1.03a 5/2003 12/36 ? 2001, giga semiconductor, inc. specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. gs8162z18a(b/d)/gs8162z 36a(b/d)/gs8162z72a(c) preliminary intermediate intermediate intermediate intermediate intermediate intermediate high z (data in) data out (q valid) high z b w b r b d r w r w d d pipeline mode data i/o state diagram current state (n) next state (n+2) transition ? input command code key transition intermediate state (n+1) notes 1. the hold command (cke low) is not shown because it prevents any state change. 2. w, r, b, and d represent input command codes as indicated in the truth tables. clock (ck) command current state intermediate ? n n+1 n+2 n+3 ??? current state and next state definition for pipeline mode data i/o state diagram next state state
rev: 1.03a 5/2003 13/36 ? 2001, giga semiconductor, inc. specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. gs8162z18a(b/d)/gs8162z 36a(b/d)/gs8162z72a(c) preliminary high z (data in) data out (q valid) high z b w b r b d r w r w d d current state (n) next state (n+1) transition ? input command code key notes 1. the hold command (cke low) is not shown because it prevents any state change. 2. w, r, b, and d represent input command codes as indicated in the truth tables. flow through mode data i/o state diagram clock (ck) command current state next state ? n n+1 n+2 n+3 ??? current state and next state definition for: pipeline and flow th rough read write c ontrol state diagram
rev: 1.03a 5/2003 14/36 ? 2001, giga semiconductor, inc. specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. gs8162z18a(b/d)/gs8162z 36a(b/d)/gs8162z72a(c) preliminary burst cycles although nbt rams are designed to sustain 100% bus bandwidth by eliminating turnaround cycle when there is transition from read to write, multiple back-t o-back reads or writes may also be performed. nbt srams provide an on-chip burst address generator that can be utilized, if desired, to further simplify burst read or write implementatio ns. the adv control pin, when driven high, commands the sram to advance the internal address counter and use the c ounter generated address to read or write the sram. the starting address for the first cy cle in a burst cycle series is loaded in to the sram by driving the adv pin low, into load mode. burst order the burst address counter wraps around to its initial state after four addresses (the loaded address and three more) have been accessed. the burst sequence is determined by the state of the linear burst order pin (lbo ). when this pin is low, a linear burst sequence is selected. when the ram is installed with the lbo pi n tied high, interleaved burst se quence is selected. see the tab les below for details. flxdrive? the zq pin allows selection between nbt ram nominal drive strength (zq low) for multi-drop bus applications and low drive strength (zq floating or high) point-to-point applications . see the output driver char acteristics chart for details. note: there arepull-up devices on the zq, scd, and ft pins and pull-down device on the zz pin, so those input pins can be unconnected and the chip will operate in the default states as specified in the above tables. enable / disable parity i/o pins this sram allows the user to configure the device to operate in parity i/o active (x18, x36, or x72) or in parity i/o inactive (x16, x32, or x64) mode. holding the pe bump low or letting it float will activ ate the 9th i/o on each byte of the ram. mode pin functions mode name pin name state function burst order control lbo l linear burst h interleaved burst output register control ft l flow through h or nc pipeline power down control zz l or nc active h standby, i dd = i sb single/dual cycle deselect control scd l dual cycle deselect h or nc single cycle deselect flxdrive output impedance control zq l high drive (low impedance) h or nc low drive (high impedance) 9th i/o enable pe l or nc activate 9th i/os h deactivate 9th i/os
rev: 1.03a 5/2003 15/36 ? 2001, giga semiconductor, inc. specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. gs8162z18a(b/d)/gs8162z 36a(b/d)/gs8162z72a(c) preliminary burst counter sequences bpr 1999.05.18 sleep mode during normal operation, zz must be pulled low, either by the us er or by its internal pull down resistor. when zz is pulled hig h, the sram will enter a power sleep mode after 2 cycles. at this time, internal stat e of the sram is preserved. when zz returns t o low, the sram operates norma lly after zz recovery time. sleep mode is a low current, power-down mode in which the device is deselected and current is reduced to i sb 2. the duration of sleep mode is dictated by the length of time the zz is in a high state. after entering sleep mode, all inputs except zz become disabled and all outputs go to high-z the zz pin is an async hronous, active high input that cau ses the device to enter sleep mo de. when the zz pin is driven high, i sb 2 is guaranteed after the time tzzi is met. because zz is an asynchronous input, pending operations or operations in progress may not be properly completed if zz is asserted. therefore, sleep mode must not be initiat ed until valid pending operations are completed. similarly, when exit ing sleep mode during tzzr, only a deselect or read commands may be applied while the sram is recovering from sleep mode. sleep mode timing diagram designing for compatibility the gsi nbt srams offer users a configurable selection between flow through mode and pipeline mode via the ft signal found on bump 5r. not all vendors offer this option, however most mark bump 5r as v dd or v ddq on pipelined parts and v ss on flow through parts. gsi nbt srams are fully compatible with these sockets. linear burst sequence note: the burst counter wraps to initial state on the 5th clock . i nterleaved burst sequence note: the burst counter wraps to initial state on the 5th clock. a[1:0] a[1:0] a[1:0] a[1:0] 1st address 00 01 10 11 2nd address 01 10 11 00 3rd address 10 11 00 01 4th address 11 00 01 10 a[1:0] a[1:0] a[1:0] a[1:0] 1st address 00 01 10 11 2nd address 01 00 11 10 3rd address 10 11 00 01 4th address 11 10 01 00 ck zz tzzr tzzh tzzs ~ ~ ~ ~ sleep ~ ~ ~ ~ ~ ~
rev: 1.03a 5/2003 16/36 ? 2001, giga semiconductor, inc. specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. gs8162z18a(b/d)/gs8162z 36a(b/d)/gs8162z72a(c) preliminary note: permanent damage to the device may occur if the absolute maximu m ratings are exceeded. operation should be restricted to recomm ended operating conditions. exposure to conditions exceeding the absolute maximum ratings, for an exte nded period of tim e, may affect reliability of this component. absolute maximum ratings (all voltages reference to v ss ) symbol description value unit v dd voltage on v dd pins ? 0.5 to 4.6 v v ddq voltage in v ddq pins ? 0.5 to 4.6 v v i/o voltage on i/o pins ? 0.5 to v ddq +0.5 ( 4.6 v max.) v v in voltage on other input pins ? 0.5 to v dd +0.5 ( 4.6 v max.) v i in input current on any pin +/ ? 20 ma i out output current on any i/o pin +/ ? 20 ma p d package power dissipation 1.5 w t stg storage temperature ? 55 to 125 o c t bias temperature under bias ? 55 to 125 o c
rev: 1.03a 5/2003 17/36 ? 2001, giga semiconductor, inc. specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. gs8162z18a(b/d)/gs8162z 36a(b/d)/gs8162z72a(c) preliminary power supply voltage ranges parameter symbol min. typ. max. unit notes 3.3 v supply voltage v dd3 3.0 3.3 3.6 v 2.5 v supply voltage v dd2 2.3 2.5 2.7 v 3.3 v v ddq i/o supply voltage v ddq3 3.0 3.3 3.6 v 2.5 v v ddq i/o supply voltage v ddq2 2.3 2.5 2.7 v notes: 1. the part numbers of industrial temperature range versions end the character ?i?. unless otherwise noted, all performance spe cifications quoted are evaluated for worst case in the temperature range marked on the device. 2. input under/overshoot voltage must be ? 2 v > vi < v ddn +2 v not to exceed 4.6 v maximum, with a pulse width not to exceed 20% tkc. v ddq3 range logic levels parameter symbol min. typ. max. unit notes v dd input high voltage v ih 2.0 ? v dd + 0.3 v1 v dd input low voltage v il ? 0.3 ? 0.8 v 1 v ddq i/o input high voltage v ihq 2.0 ? v ddq + 0.3 v1,3 v ddq i/o input low voltage v ilq ? 0.3 ? 0.8 v 1,3 notes: 1. the part numbers of industrial temperature range versions end the character ?i?. unless otherwise noted, all performance spe cifications quoted are evaluated for worst case in the temperature range marked on the device. 2. input under/overshoot voltage must be ? 2 v > vi < v ddn +2 v not to exceed 4.6 v maximum, with a pulse width not to exceed 20% tkc. 3. v ihq (max) is voltage on v ddq pins plus 0.3 v. v ddq2 range logic levels parameter symbol min. typ. max. unit notes v dd input high voltage v ih 0.6*v dd ? v dd + 0.3 v1 v dd input low voltage v il ? 0.3 ? 0.3*v dd v1 v ddq i/o input high voltage v ihq 0.6*v dd ? v ddq + 0.3 v1,3 v ddq i/o input low voltage v ilq ? 0.3 ? 0.3*v dd v1,3 notes: 1. the part numbers of industrial temperature range versions end the character ?i?. unless otherwise noted, all performance spe cifications quoted are evaluated for worst case in the temperature range marked on the device. 2. input under/overshoot voltage must be ? 2 v > vi < v ddn +2 v not to exceed 4.6 v maximum, with a pulse width not to exceed 20% tkc. 3. v ihq (max) is voltage on v ddq pins plus 0.3 v.
rev: 1.03a 5/2003 18/36 ? 2001, giga semiconductor, inc. specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. gs8162z18a(b/d)/gs8162z 36a(b/d)/gs8162z72a(c) preliminary note: these parameters are sample tested. recommended operating temperatures parameter symbol min. typ. max. unit notes ambient temperature (com mercial range versions) t a 02570 c2 ambient temperature (industrial range versions) t a ? 40 25 85 c2 note: 1. the part numbers of industrial temperature range versions end the character ?i?. unless otherwise noted, all performance spe cifications quoted are evaluated for worst case in the temperature range marked on the device. 2. input under/overshoot voltage must be ? 2 v > vi < v ddn +2 v not to exceed 4.6 v maximum, with a pulse width not to exceed 20% tkc. capacitance (t a = 25 o c, f = 1 mh z , v dd = 2.5 v) parameter symbol test conditions typ. max. unit input capacitance c in v in = 0 v 45pf input/output capacitance c i/o v out = 0 v 67pf 20% tkc v ss ? 2.0 v 50% v ss v ih undershoot measurement and timing overshoot measurement and timing 20% tkc v dd + 2.0 v 50% v dd v il
rev: 1.03a 5/2003 19/36 ? 2001, giga semiconductor, inc. specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. gs8162z18a(b/d)/gs8162z 36a(b/d)/gs8162z72a(c) preliminary ac test conditions parameter conditions input high level v dd ? 0.2 v input low level 0.2 v input slew rate 1 v/ns input reference level v dd /2 output reference level v ddq /2 output load fig. 1 notes: 1. include scope and jig capacitance. 2. test conditions as specified with output loading as shown in fig. 1 unless otherwise noted. 3. device is deselected as defined by the truth table. dc electrical characteristics parameter symbol test conditions min max input leakage current (except mode pins) i il v in = 0 to v dd ? 1 ua 1 ua zz and pe input current i in1 v dd v in v ih 0 v v in v ih ? 1 ua ? 1 ua 1 ua 100 ua ft , zq input current i in2 v dd v in v il 0 v v in v il ? 100 ua ? 1 ua 1 ua 1 ua output leakage current i ol output disable, v out = 0 to v dd ? 1 ua 1 ua output high voltage v oh2 i oh = ? 8 ma, v ddq = 2.375 v 1.7 v ? output high voltage v oh3 i oh = ? 8 ma, v ddq = 3.135 v 2.4 v ? output low voltage v ol i ol = 8 ma ? 0.4 v dq v ddq/2 50 ? 30pf * output load 1 * distributed test jig capacitance
rev: 1.03a 5/2003 20/36 ? 2001, giga semiconductor, inc. specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. gs8162z18a(b/d)/gs8162z 36a(b/d)/gs8162z72a(c) preliminary operating currents notes: 1. i dd and i ddq apply to any combination of v dd3 , v dd2 , v ddq3 , and v ddq2 operation. 2. all parameters listed are worst case scenario. parameter test conditions mode symbol -300 -250 -200 -150 unit 0 to 70c ? 40 to 85c 0 to 70c ? 40 to 85c 0 to 70c ? 40 to 85c 0 to 70c ? 40 to 85c operating current device selected; all other inputs v ih o r v il output open (x72) pipeline i dd i ddq 415 80 425 80 350 75 360 75 290 55 300 55 230 40 240 40 ma flow through i dd i ddq 290 55 300 55 265 50 275 50 230 45 240 45 210 40 220 40 ma (x32/ x36) pipeline i dd i ddq 345 45 355 45 290 40 300 40 240 30 250 30 190 20 200 20 ma flow through i dd i ddq 240 30 250 30 220 20 230 20 190 15 200 15 175 15 185 15 ma (x18) pipeline i dd i ddq 310 25 320 25 260 20 270 20 215 15 225 15 170 15 180 15 ma flow through i dd i ddq 215 15 225 15 200 10 210 10 175 10 185 10 160 10 170 10 ma standby current zz v dd ? 0.2 v ? pipeline i sb 40 50 40 50 40 50 40 50 ma flow through i sb 40 50 40 50 40 50 40 50 ma deselect current device deselected; all other inputs v ih or v il ? pipeline i dd 85 90 85 90 75 80 60 65 ma flow through i dd 60 65 60 65 50 55 50 55 ma
rev: 1.03a 5/2003 21/36 ? 2001, giga semiconductor, inc. specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. gs8162z18a(b/d)/gs8162z 36a(b/d)/gs8162z72a(c) preliminary ac electrical characteristics notes: 1. these parameters are sampled and are not 100% tested. 2. zz is an asynchronous signal. however, in order to be recognize d on any given clock cycle, zz must meet the specified setup a nd hold times as specified above. parameter symbol -300 -250 -200 -150 unit min max min max min max min max pipeline clock cycle time tkc 3.3 ? 4.0 ? 5.0 ? 6.7 ? ns clock to output valid (x18/x36) tkq ? 2.5 ? 2.5 ? 3.0 ? 3.8 ns clock to output valid (x72) tkq ? 2.8 ? 3.0 ? 3.0 ? 3.8 ns clock to output invalid tkqx 1.5 ? 1.5 ? 1.5 ? 1.5 ? ns clock to output in low-z tlz 1 1.5 ? 1.5 ? 1.5 ? 1.5 ? ns setup time ts 1.0 ? 1.2 ? 1.4 ? 1.5 ? ns hold time th 0.1 ? 0.2 ? 0.4 ? 0.5 ? ns flow through clock cycle time tkc 5.0 ? 5.5 ? 6.5 ? 7.5 ? ns clock to output valid tkq ? 5.0 ? 5.5 ? 6.5 ? 7.5 ns clock to output invalid tkqx 3.0 ? 3.0 ? 3.0 ? 3.0 ? ns clock to output in low-z tlz 1 3.0 ? 3.0 ? 3.0 ? 3.0 ? ns setup time ts 1.4 ? 1.5 ? 1.5 ? 1.5 ? ns hold time th 0.4 ? 0.5 ? 0.5 ? 0.5 ? ns clock high time tkh 1.3 ? 1.3 ? 1.3 ? 1.5 ? ns clock low time tkl 1.5 ? 1.5 ? 1.5 ? 1.7 ? ns clock to output in high-z (x18/x36) thz 1 1.5 2.5 1.5 2.5 1.5 3.0 1.5 3.0 ns clock to output in high-z (x72) thz 1 1.5 2.8 1.5 3.0 1.5 3.0 1.5 3.0 ns g to output valid (x18/x36) toe ? 2.5 ? 2.5 ? 3.0 ? 3.8 ns g to output valid (x72) toe ? 2.8 ? 3.0 ? 3.0 ? 3.8 ns g to output in low-z tolz 1 0 ? 0 ? 0 ? 0 ? ns g to output in high-z (x18/x36) tohz 1 ? 2.5 ? 2.5 ? 3.0 ? 3.8 ns g to output in high-z (x72) tohz 1 ? 2.8 ? 3.0 ? 3.0 ? 3.8 ns zz setup time tzzs 2 5 ? 5 ? 5 ? 5 ? ns zz hold time tzzh 2 1 ? 1 ? 1 ? 1 ? ns zz recovery tzzr 20 ? 20 ? 20 ? 20 ? ns
rev: 1.03a 5/2003 22/36 ? 2001, giga semiconductor, inc. specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. gs8162z18a(b/d)/gs8162z 36a(b/d)/gs8162z72a(c) preliminary pipeline mode timing (nbt) write a read b suspend read c write d suspend1 write read e deselect thz tkqx tkq tlz ts tkqx tkq tkq th ts th ts th ts th ts th ts th ts th ts tkc tkc tkl tkl tkh tkh ab cd d(a) q(b) q(c) d(d) q(e) e ck cke e adv w b n a0?an dq
rev: 1.03a 5/2003 23/36 ? 2001, giga semiconductor, inc. specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. gs8162z18a(b/d)/gs8162z 36a(b/d)/gs8162z72a(c) preliminary flow through mode timing (nbt) write a read b suspend read c write d1 suspend1 write read e deselect thz tkqx tlz thz tkqx tkq th ts th ts th ts th ts th ts th ts th ts tkc tkc tkl tkl tkh tkh ab cd e d(a) q(b) q(c) d(d) q(e) ck cke e adv w b n a0?an dq
rev: 1.03a 5/2003 24/36 ? 2001, giga semiconductor, inc. specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. gs8162z18a(b/d)/gs8162z 36a(b/d)/gs8162z72a(c) preliminary jtag port operation overview the jtag port on this ram operates in a manner that is co mpliant with ieee standard 1149. 1-1990, a serial boundary scan interface standard (commonly referred to as jtag) . the jtag port input interface levels scale with v dd . the jtag output drivers are powered by v ddq . disabling the jtag port it is possible to use this device without utilizing the jtag port. the port is reset at power-up and will remain inactive unles s clocked. tck, tdi, and tms are designed with internal pull-up circuits.to assure normal operation of the ram with the jtag port unused, tck, tdi, and tms may be left floating or tied to either v dd or v ss . tdo should be left unconnected. jtag port registers overview the various jtag registers, refered to as test access port ortap registers, are selected (one at a time) via the sequences of 1 s and 0s applied to tms as tck is strobed. each of the tap registers is a serial shift register that captures serial input data on th e rising edge of tck and pushes serial data out on the next falling edge of tck. when a register is se lected, it is placed between the tdi and tdo pins. instruction register the instruction register holds the instructio ns that are executed by the tap controller when it is moved into the run, test/idl e, or the various data register states. instructions are 3 bits long. th e instruction register can be lo aded when it is placed betwee n the tdi and tdo pins. the instruction register is automatically preloa ded with the idcode instruction at power-up or whenever the controller is placed in test-logic-reset state. jtag pin descriptions pin pin name i/o description tck test clock in clocks all tap events. all i nputs are captured on the rising edge of tck and all outputs propagate from the falling edge of tck. tms test mode select in the tms input is sampled on the rising edge of tck. this is the command input for the tap controller state machine. an undriven tms input wi ll produce the same result as a logic one input level. tdi test data in in the tdi input is sampled on the rising edge of tck. this is the input side of the serial registers placed between tdi and tdo. the register pl aced between tdi and tdo is determined by the state of the tap controller state machine and the instruction that is currently loaded in the tap instruction register (refer to the tap controll er state diagram). an undriven tdi pin will produce the same result as a logic one input level. tdo test data out out output that is active depending on the state of the tap state machine. output changes in response to the falling edge of tck. this is the out put side of the serial registers placed between tdi and tdo. note: this device does not have a trst (tap rese t) pin. trst is optional in ieee 1149.1. the test-logic-reset state is entered while tms is held high for five rising edges of tck. the tap cont roller is also reset aut omaticly at power-up.
rev: 1.03a 5/2003 25/36 ? 2001, giga semiconductor, inc. specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. gs8162z18a(b/d)/gs8162z 36a(b/d)/gs8162z72a(c) preliminary bypass register the bypass register is a single bit register that can be placed between tdi and tdo. it allows serial test data to be passed th rough the ram?s jtag port to another device in th e scan chain with as little delay as possible. boundary scan register the boundary scan register is a collection of flip flops that can be preset by the logic level found on the ram?s input or i/o pins. the flip flops are then daisy chained together so the levels found can be shifted serially out of the jtag port?s tdo pin. the boundary scan register also includes a number of place holder flip fl ops (always set to a logic 1). the relationship between t he device pins and the bits in the boundary scan register is de scribed in the scan order table following. the boundary scan register, under the control of the tap contro ller, is loaded with the contents of th e rams i/o ring when the controller is in capture-dr state and then is placed between the tdi and tdo pins when the controller is moved to shift- dr state. sample-z, sample/preload and extest instructions can be us ed to activate the boundary scan register. jtag tap block diagram identification (id) register the id register is a 32-bit register that is loaded with a device and vendor specific 32-bit code when the controller is put in capture-dr state with the idcode command loaded in the instruction register. the c ode is loaded from a 32-bit on-chip rom. it describes various attributes of the ram as indicated below. the register is then placed between the tdi and tdo pins when th e controller is moved into shift- dr state. bit 0 in the register is the lsb and the first to reach tdo when shifting begins. instruction register id code register boundary scan register 0 1 2 0 1 2 31 30 29 0 1 2 n 0 bypass register tdi tdo tms tck test access port (tap) controller
rev: 1.03a 5/2003 26/36 ? 2001, giga semiconductor, inc. specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. gs8162z18a(b/d)/gs8162z 36a(b/d)/gs8162z72a(c) preliminary tap controller instruction set overview there are two classes of instructions defi ned in the standard 1149.1-1990; the standard (public) instructions, and device speci fic (private) instructions. some public instructions are mandatory for 1149.1 compliance. optional public instructions must be implemented in prescribed ways. the tap on this device may be used to monitor all input and i/o pads, and can be used to load address, data or control signals into the ram or to preload the i/o buffers. when the tap controller is placed in captur e-ir state the two least significant bits of the instruction regi ster are loaded wit h 01. when the controller is moved to the shift-ir state the instructi on register is placed between tdi and tdo. in this state the de sired instruction is serially loaded through the tdi input (while the previous contents are shifted out at tdo). for all instructions , the tap executes newly loaded instructions only when the controller is moved to update-ir state. the tap instruction set for this device is listed in the following table. id register contents die revision code not used i/o configuration gsi technology jedec vendor id code presence register bit # 31302928272625242322212019181716151413121110987654321 0 x72 xxxx0000000000001001000110110011 x36 xxxx0000000000001000000110110011 x32 xxxx0000000000001100000110110011 x18 xxxx0000000000001010000110110011 x16 xxxx0000000000001110000110110011
rev: 1.03a 5/2003 27/36 ? 2001, giga semiconductor, inc. specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. gs8162z18a(b/d)/gs8162z 36a(b/d)/gs8162z72a(c) preliminary jtag tap controller state diagram instruction descriptions bypass when the bypass instruction is loaded in the instruction register the bypass register is placed between tdi and tdo. this occur s when the tap controller is moved to the shift-dr state. this allo ws the board level scan path to be shortened to facilitate testing of other devices in the scan path. sample/preload sample/preload is a standard 1149.1 mandatory public instruction. when the sample / preload instruction is loaded in the instru c- tion register, moving the tap controller into the capture-dr state loads the data in the rams input and i/o buffers into the bo undary scan register. boundary scan register locations are not associated with an input or i/o pin, and are loaded with the default state i dentified in the boundary scan chain table at the end of this section of the dat asheet. because the ram clock is independent from the tap clock (tck) it is possible for the tap to attempt to capture the i/o ring conten ts while the input buffers are in transition (i.e. in a metast able state). although allowing the tap to sample metastable inputs will not harm the device, repeatable results cannot be expected. ram input signals must be stabilized for long enough to meet the taps input data capture set- up plus hold time (tts plus tth). the rams clock inputs need not be paused for any other tap operation except capturing the i/o ring contents into the boundary scan r egister. moving the controlle r to shift- dr state then places the boundary scan register between t he tdi and tdo pins. extest extest is an ieee 1149.1 mandatory public instruction. it is to be executed whenever the instruct ion register is loaded with al l logic 0s. the extest command does not block or override the ram?s input pins; therefore, the ram?s in ternal state is still determined by its input pins. select dr capture dr shift dr exit1 dr pause dr exit2 dr update dr select ir capture ir shift ir exit1 ir pause ir exit2 ir update ir test logic reset run test idle 0 0 1 0 1 1 0 0 1 1 1 0 0 1 1 0 0 0 0 1 1 0 0 1 1 0 0 0 1 11 1
rev: 1.03a 5/2003 28/36 ? 2001, giga semiconductor, inc. specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. gs8162z18a(b/d)/gs8162z 36a(b/d)/gs8162z72a(c) preliminary typically, the boundary scan register is loaded with the desired pa ttern of data with the sample/preload command. then the exte st command is used to output the boundary scan register?s contents, in parallel, on the ram?s data output drivers on the falling e dge of tck when the controller is in the update-ir state. alternately, the boundary scan register may be loaded in parallel using the extest co mmand. when the extest instruction is sele cted, the sate of all the ram?s input and i/o pins, as well as the default va lues at scan register locations not associated with a pin, a re transferred in parallel into the boundary scan register on the rising edge of tck in the capture-dr state, the ra m?s output pins drive out the value of the boundary scan register location with wh ich each output pin is associated. idcode the idcode instruction causes the id rom to be loaded into the id register when the controller is in capture-dr mode and places the id register between the tdi and tdo pins in sh ift-dr mode. the idcode instruction is t he default instruction loaded in at power up and any time the controller is placed in the test-logic-reset state. sample-z if the sample-z instruction is loaded in the instruction register , all ram outputs are forced to an inactive drive state (high- z) and the bound- ary scan register is connected between tdi and tdo when the tap controller is moved to the shift-dr state. rfu these instructions are reserved for future use. in this device they replicate the bypass instruction. jtag tap instruction set summary instruction code description notes extest 000 places the boundary scan register between tdi and tdo. 1 idcode 001 preloads id register and places it between tdi and tdo. 1, 2 sample-z 010 captures i/o ring contents. places the b oundary scan register between tdi and tdo. forces all ram output drivers to high-z. 1 rfu 011 do not use this instruction; reserved for future use. replicates bypass instruction. places bypass register between tdi and tdo. 1 sample/ preload 100 captures i/o ring contents. places the b oundary scan register between tdi and tdo. 1 gsi 101 gsi private instruction. 1 rfu 110 do not use this instruction; reserved for future use. replicates bypass instruction. places bypass register between tdi and tdo. 1 bypass 111 places bypass register between tdi and tdo. 1 notes: 1. instruction codes expressed in binary, msb on left, lsb on right. 2. default instruction automatically loaded at power-up and in test-logic-reset state.
rev: 1.03a 5/2003 29/36 ? 2001, giga semiconductor, inc. specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. gs8162z18a(b/d)/gs8162z 36a(b/d)/gs8162z72a(c) preliminary jtag port recommended operating conditions and dc characteristics parameter symbol min. max. unit notes 3.3 v test port input high voltage v ihj3 2.0 v dd3 +0.3 v1 3.3 v test port input low voltage v ilj3 ? 0.3 0.8 v 1 2.5 v test port input high voltage v ihj2 0.6 * v dd2 v dd2 +0.3 v1 2.5 v test port input low voltage v ilj2 ? 0.3 0.3 * v dd2 v1 tms, tck and tdi input leakage current i inhj ? 300 1 ua 2 tms, tck and tdi input leakage current i inlj ? 1 100 ua 3 tdo output leakage current i olj ? 11ua4 test port output high voltage v ohj 1.7 ? v5, 6 test port output low voltage v olj ? 0.4 v 5, 7 test port output cmos high v ohjc v ddq ? 100 mv ? v5, 8 test port output cmos low v oljc ? 100 mv v 5, 9 notes: 1. input under/overshoot voltage must be ? 2 v > vi < v ddn +2 v not to exceed 4.6 v maximum, with a pulse width not to exceed 20% ttkc. 2. v ilj v in v ddn 3. 0 v v in v iljn 4. output disable, v out = 0 to v ddn 5. the tdo output driver is served by the v ddq supply. 6. i ohj = ? 4 ma 7. i olj = + 4 ma 8. i ohjc = ?100 ua 9. i ohjc = +100 ua notes: 1. include scope and jig capacitance. 2. test conditions as as shown unless otherwise noted. jtag port ac test conditions parameter conditions input high level v dd ? 0.2 v input low level 0.2 v input slew rate 1 v/ns input reference level v ddq /2 output reference level v ddq /2 dq v ddq /2 50 ? 30pf * jtag port ac test load * distributed test jig capacitance
rev: 1.03a 5/2003 30/36 ? 2001, giga semiconductor, inc. specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. gs8162z18a(b/d)/gs8162z 36a(b/d)/gs8162z72a(c) preliminary jtag port timing diagram jtag port ac electrical characteristics boundary scan (bsdl files) for information regarding the boundary scan chain, or to obta in bsdl files for this part, please contact our applications engineering department at: apps@gsitechnology.com . parameter symbol min max unit tck cycle time ttkc 50 ? ns tck low to tdo valid ttkq ? 20 ns tck high pulse width ttkh 20 ? ns tck low pulse width ttkl 20 ? ns tdi & tms set up time tts 10 ? ns tdi & tms hold time tth 10 ? ns ttkq tts tth ttkh ttkl tck tms tdi tdo ttkc
rev: 1.03a 5/2003 31/36 ? 2001, giga semiconductor, inc. specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. gs8162z18a(b/d)/gs8162z 36a(b/d)/gs8162z72a(c) preliminary 209 bga package dr awing (package c) 14 mm x 22 mm body, 1.0 mm bump pitch, 11 x 19 bump array symbol min typ max units a ??1.70mm a1 0.40 0.50 0.60 mm ? b 0.50 0.60 0.70 mm c 0.31 0.36 0.38 mm d 21.9 22.0 22.1 mm d1 ? 18.0 (bsc) ? mm e 13.9 14.0 14.1 mm e1 ? 10.0 (bsc) ? mm e ? 1.00 (bsc) ? mm aaa ?0.15?mm rev 1.0 a a1 c ? b e e e e1 d1 d aaa bottom view side view
rev: 1.03a 5/2003 32/36 ? 2001, giga semiconductor, inc. specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. gs8162z18a(b/d)/gs8162z 36a(b/d)/gs8162z72a(c) preliminary package dimensions?165- bump fpbga (package d) a b c d e f g h i j k l m n p r a b c d e f g h i j k l m n p r 1 2 3 4 5 6 7 8 9 10 11 11 10 9 8 7 6 5 4 3 2 1 a1 corner top view a1 corner bottom view 1.0 1.0 10.0 1.0 1.0 14.0 130.07 150.07 a b 0.20(4x) ?0.10 ?0.25 c c a b m m ?0.40~0.50 (165x) c seating plane 0.15 c 0.25~0.40 1.20 max. 0.450.05 0.25 c (0.26)
rev: 1.03a 5/2003 33/36 ? 2001, giga semiconductor, inc. specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. gs8162z18a(b/d)/gs8162z 36a(b/d)/gs8162z72a(c) preliminary package dimensions ? 119-pin pbga (package b) bpr 1999.05.18 a b pin 1 corner k e f ct a b c d e f g h j k l m n p r t u g s d 1 2 3 4 5 6 7 package dimensions?119-pin pbga unit: mm symbol description min. nom. max a width 13.9 14.0 14.1 b length 21.9 22.0 22.1 c package height (including ball) 1.73 1.86 1.99 d ball size 0.60 0.75 0.90 e ball height 0.50 0.60 0.70 f package height (excluding balls) 1.16 1.26 1.36 g width between balls 1.27 k package height above board 0.65 0.70 0.75 r width of package between balls 7.62 s length of package between balls 20.32 t variance of ball height 0.15 bottom view r top view side view a b c d e f g h j k l m n p r t u
rev: 1.03a 5/2003 34/36 ? 2001, giga semiconductor, inc. specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. gs8162z18a(b/d)/gs8162z 36a(b/d)/gs8162z72a(c) preliminary ordering information ? gsi nbt synchronous sram org part number 1 type package speed 2 (mhz/ns) t a 3 status 1m x 18 gs8162z18ab-300 pipeline/flow through 119 bga 300/5 c 1m x 18 gs8162z18ab-250 pipeline/flow through 119 bga 250/5.5 c 1m x 18 gs8162z18ab-200 pipeline/flow through 119 bga 200/6.5 c 1m x 18 gs8162z18ab-150 pipeline/flow through 119 bga 150/7.5 c 512k x 36 gs8162z36ab-300 pipeline/flow through 119 bga 300/5 c 512k x 36 gs8162z36ab-250 pipeline/flow through 119 bga 250/5.5 c 512k x 36 gs8162z36ab-200 pipeline/flow through 119 bga 200/6.5 c 512k x 36 gs8162z36ab-150 pipeline/flow through 119 bga 150/7.5 c 1m x 18 gs8162z18ad-300 pipeline/flow through 165 bga 300/5 c 1m x 18 gs8162z18ad-250 pipeline/flow through 165 bga 250/5.5 c 1m x 18 gs8162z18ad-200 pipeline/flow through 165 bga 200/6.5 c 1m x 18 gs8162z18ad-150 pipeline/flow through 165 bga 150/7.5 c 512k x 36 gs8162z36ad-300 pipeline/flow through 165 bga 300/5 c 512k x 36 gs8162z36ad-250 pipeline/flow through 165 bga 250/5.5 c 512k x 36 gs8162z36ad-200 pipeline/flow through 165 bga 200/6.5 c 512k x 36 gs8162z36ad-150 pipeline/flow through 165 bga 150/7.5 c 256k x 72 gs8162z72ac-300 pipeline/flow through 209 bga 300/5 c 256k x 72 gs8162z72ac-250 pipeline/flow through 209 bga 250/5.5 c 256k x 72 gs8162z72ac-200 pipeline/flow through 209 bga 200/6.5 c 256k x 72 gs8162z72ac-150 pipeline/flow through 209 bga 150/7.5 c 1m x 18 gs8162z18ab-300i pipeline/flow through 119 bga 300/5 i 1m x 18 gs8162z18ab-250i pipeline/flow through 119 bga 250/5.5 i 1m x 18 gs8162z18ab-200i pipeline/flow through 119 bga 200/6.5 i 1m x 18 gs8162z18ab-150i pipeline/flow through 119 bga 150/7.5 i 512k x 36 gs8162z36ab-300i pipeline/flow through 119 bga 300/5 i 512k x 36 gs8162z36ab-250i pipeline/flow through 119 bga 250/5.5 i 512k x 36 gs8162z36ab-200i pipeline/flow through 119 bga 200/6.5 i 512k x 36 gs8162z36ab-150i pipeline/flow through 119 bga 150/7.5 i 1m x 18 gs8162z18ad-300i pipeline/flow through 165 bga 300/5 i 1m x 18 gs8162z18ad-250i pipeline/flow through 165 bga 250/5.5 i notes: 1. customers requiring delivery in tape and r eel should add the character ?t? to the end of the part number. example: gs8162z36a b-200it. 2. the speed column indicates the cycle frequenc y (mhz) of the device in pipeline mode and the latency (ns) in flow through mod e. each device is pipeline/flow through mode-selectable by the user. 3. t a = c = commercial temperature range. t a = i = industrial temperature range. 4. gsi offers other versions this type of device in many different configurations and with a variety of different features, onl y some of which are covered in this data sheet. see the gs i technology web site (www.gsitechnology.com ) for a complete listing of current offerings
rev: 1.03a 5/2003 35/36 ? 2001, giga semiconductor, inc. specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. gs8162z18a(b/d)/gs8162z 36a(b/d)/gs8162z72a(c) preliminary 1m x 18 gs8162z18ad-200i pipeline/flow through 165 bga 200/6.5 i 1m x 18 gs8162z18ad-150i pipeline/flow through 165 bga 150/7.5 i 512k x 36 gs8162z36ad-300i pipeline/flow through 165 bga 300/5 i 512k x 36 gs8162z36ad-250i pipeline/flow through 165 bga 250/5.5 i 512k x 36 gs8162z36ad-200i pipeline/flow through 165 bga 200/6.5 i 512k x 36 gs8162z36ad-150i pipeline/flow through 165 bga 150/7.5 i 256k x 72 gs8162z72ac-30i pipeline/flow through 209 bga 300/5 i 256k x 72 gs8162z72ac-250i pipeline/flow through 209 bga 250/5.5 i 256k x 72 gs8162z72ac-200i pipeline/flow through 209 bga 200/6.5 i 256k x 72 gs8162z72ac-150i pipeline/flow through 209 bga 150/7.5 i org part number 1 type package speed 2 (mhz/ns) t a 3 status notes: 1. customers requiring delivery in tape and r eel should add the character ?t? to the end of the part number. example: gs8162z36a b-200it. 2. the speed column indicates the cycle frequenc y (mhz) of the device in pipeline mode and the latency (ns) in flow through mod e. each device is pipeline/flow through mode-selectable by the user. 3. t a = c = commercial temperature range. t a = i = industrial temperature range. 4. gsi offers other versions this type of device in many different configurations and with a variety of different features, onl y some of which are covered in this data sheet. see the gs i technology web site (www.gsitechnology.com ) for a complete listing of current offerings
rev: 1.03a 5/2003 36/36 ? 2001, giga semiconductor, inc. specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. gs8162z18a(b/d)/gs8162z 36a(b/d)/gs8162z72a(c) preliminary 18mb sync sram datasheet revision history ds/daterev. code: old; new types of changes format or content page;revisions;reason gs8162z18a_r1 ? creation of new datasheet 8162z18a_r1; 8162z18_r1_01 content ? updated flow through power numbers in table on page 1 and operating currents table ? updated pipeline and flow through numbers in ac charac- teristics table ? added 165-bump bga package, pinout, and pinout descrip- tion ? removed bytesafe pins and references ? updated zz timing diagram ? updated ac test conditions table and removed output load 2 diagram 8162z18a_r1_01; 8162z18_r1_02 content ? removed parity i/o bit designation from 165 bga pinout ? updated both 209 bga and 119 bga pin description tables ? removed bsr table ? removed pin locations from pin description tables gs8162zxxa_r1_02; gs8162zxxa_r1_03 content ? entire datasheet rewritten due to design changes

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